1. Field of the Invention
The present invention relates to a multilayer chip capacitor, and, more particularly, to a multilayer chip capacitor, designed to avoid occurrence of cracks caused by a thickness difference and short circuit caused by misalignment of cutting lines, thereby enhancing reliability of devices, and a method for manufacturing the same.
2. Description of the Related Art
Generally, a multilayer chip capacitor (MLCC) comprises a plurality of dielectric layers referred to as ceramic green sheets and internal electrodes formed between the plurality of dielectric layers. Since such a multilayer chip capacitor can realize a higher electrostatic capacitance with a small size while being easily mounted on a substrate, it is widely used as a capacitive component of various electronic devices.
Such a multilayer chip capacitor is manufactured by alternately stacking dielectric layers having two internal electrodes of different polarities printed thereon to form a stack, compressing and sintering the stack, and then forming terminal electrodes at opposite ends of the stack. At this time, when forming the internal electrodes on the dielectric layers, margins are provided to each of the dielectric layers in a width direction of the internal electrode in order to prevent electrical short while protecting the internal electrodes. Accordingly, in view of the overall appearance of the chip capacitor, a thickness difference occurs between a central portion of the chip capacitor where the internal electrodes are formed and both sides of the chip capacitor where the margins are provided. Such a thickness difference of the chip capacitor causes cracks of the chip capacitor, in particular, during a sintering process, and is a negative influence on reliability of the capacitor.
FIG. 1 is a plan view illustrating a first internal electrode and a second internal electrode of a conventional multilayer chip capacitor. Referring to FIG. 1, the first and second internal electrodes 22 and 23 are printed on dielectric layers 12 and 13 generally referred to as ceramic green sheets. The first and second internal electrodes 22 and 23 extend longitudinally (an L-direction) from one end of the dielectric layers 12 and 13 towards the other end thereof, respectively. The lengths of the internal electrodes 22 and 23 are shorter than those of the dielectric layers 12 and 13, so that each of the internal electrodes is exposed only at one end of the dielectric layers 12 and 13, and is not exposed at the other end thereof. As a result, the dielectric layers 12 and 13 have longitudinal (L-direction) margin portions 32b and 33b of a predetermined size y, respectively. Additionally, the widths of the internal electrodes 22 and 23 are shorter than those of the dielectric layers 12 and 13, so that the dielectric layers 12 and 13 have widthwise (W-direction) margin portions 32a and 32b of a predetermined size x at both sides thereof, respectively. Herein, the term “widthwise (or W-direction) margin portion” means a margin portion between an edge of the dielectric layer and that of the internal electrode, and refers to a portion extending over the entire length of the dielectric layer. The W-direction margin portions 32a and 32b are needed to prevent electrical short while protecting the internal electrodes.
Meanwhile, when the stack is produced by alternately stacking and compressing the dielectric layers with the internal electrodes 22 and 23 formed thereon, the W-direction margin portions 32a and 33a cause a thickness difference to occur between the center of the chip capacitor and both sides thereof. In FIG. 2, a non-uniform thickness of the capacitor is illustrated. FIG. 2 is a cross section taken along line A-A′ of FIG. 1, illustrating a stack of the dielectric layers having the internal electrodes formed thereon. The stack 100a of FIG. 2 is prepared by alternately stacking the dielectric layers 12 having the first internal electrodes 22 formed thereon and the dielectric layers 13 having the second internal electrodes 23 formed thereon. As shown in FIG. 2, a thickness t2 of the stack at the center of the internal electrodes is greater than a thickness t1 of the stack at the widthwise margin portions of the stack where the electrodes are not formed. When sintering the stack 100a having such a thickness difference, the thickness difference is further increased, causing lots of cracks to be created on the sintered stack 100b. Accordingly, when completely manufacturing the multilayer chip capacitor by forming the external electrodes on the stack, the multilayer chip capacitor is likely to malfunction due to the cracks.
In order to solve the problem resulting from the thickness difference, an approach has been suggested, wherein the electrodes are formed as thin as possible by reducing contents of metal, such as Ni, in conductive paste upon screen printing of the electrodes. However, it is difficult to print internal electrodes having a thickness of about 1 μm with current screen printing technology. On the other hand, although an approach has been suggested, wherein the thickness difference is complemented by printing dielectric slurries on a portion where the thickness difference occurs, this approach requires additional processes, and fails to completely solve the problem of cracks resulting from the thickness difference.
Additionally, in order to solve the problem caused by the thickness difference, U.S. Pat. No. 5,144,527 discloses an approach wherein the dielectric layers are stacked after forming the internal electrodes thereon without providing the W-direction margin portions. According to the disclosure, after stacking the dielectric layers, coating is performed on a drawing portion of the internal electrodes in order to protect the drawing portion during wet etching, and then wet etching is performed to form the W-direction margin portions. As such, due to complicated processes, this method is not only ineffective in terms of cost and time, but also difficult to secure uniformity of wet etching.